SH7721 datasheet(654/1524 Pages) RENESAS

Part #	SH7721

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

PDF	1524 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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654 / 1524 page

Section 18

Serial Communication Interface with FIFO (SCIF)

Rev. 3.00 Jan. 18, 2008 Page 592 of 1458

REJ09B0033-0300

Bit

Bit Name

Initial Value

R/W

Description

CHR

R/W

Character Length

Selects seven-bit or eight-bit data.

This bit is only valid in asynchronous mode. In

synchronous mode, the data length is always eight

bits, regardless of the CHR setting.

0: Eight-bit data

1: Seven-bit data*

Note:

When seven-bit data is selected, the MSB

(bit 7) in SCFTDR is not transmitted.

R/W

Parity Enable

Selects whether to add a parity bit to transmit data

and to check the parity of receive data. This setting is

only valid in asynchronous mode. In synchronous

mode, parity bit addition and checking is not

performed, regardless of the PE setting.

0: Parity bit not added or checked

1: Parity bit added and checked

Note:

When PE is set to 1, an even or odd parity

bit is added to transmit data, depending on

the parity mode (O/E) setting. Receive

data parity is checked according to the

even/odd (O/E) mode setting.

SH7721 Datasheet(PDF) 654 Page - Renesas Technology Corp