SH7721 datasheet(657/1524 Pages) RENESAS

657 / 1524 page

Section 18

Serial Communication Interface with FIFO (SCIF)

Rev. 3.00 Jan. 18, 2008 Page 595 of 1458

REJ09B0033-0300

18.3.6

Serial Control Register (SCSCR)

SCSCR is a 16-bit readable/writable register that operates the SCI transmitter/receiver,

enables/disables interrupt requests, and selects the transmit/receive clock source.

Bit

Bit Name

Initial Value R/W

Description

TDRQE

R/W

Transmit Data Transfer Request Enable

Selects whether to issue the transmit-FIFO-data-

empty interrupt request or DMA transfer request when

TIE = 1 and transmit FIFO empty interrupt is

generated at the transmission.

0: Interrupt request is issued to CPU

1: Transmit data transfer request is issued to DMAC

RDRQE

R/W

Receive Data Transfer Request Enable

Selects whether to issue the receive-FIFO-data-full

interrupt or DMA transfer request when RIE = 1 and

receive FIFO data full interrupt is generated at the

reception.

0: Interrupt request is issued to CPU

1: Receive data transfer request is issued to DMAC

13,12



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

TSIE

R/W

Transmit Data Stop Interrupt Enable

Enables or disables the generation of the transmit-

data-stop interrupt requested when the TSE bit in

SCFCR is enabled and the TSF flag in SCSSR is set

to 1.

0: The transmit-data-stop-interrupt disabled*

1: The transmit-data-stop-interrupt enabled

Note:

The transmit data stop interrupt request is

cleared by reading the TSF flag after it has

been set to 1, then clearing the flag to 0,

or clearing the TSIE bit to 0.

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