SH7721 datasheet(661/1524 Pages) RENESAS

661 / 1524 page

Section 18

Serial Communication Interface with FIFO (SCIF)

Rev. 3.00 Jan. 18, 2008 Page 599 of 1458

REJ09B0033-0300

18.3.7

FIFO Error Count Register (SCFER)

SCFER is a 16-bit read-only register that indicates the number of receive data errors (framing

error/parity error).

Bit

Bit Name

Initial value R/W

Description

15,14



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

PER5

PER4

PER3

PER2

PER1

PER0

Parity Error

Indicates the number of data, in which parity errors

are generated, in receive data stored in the receive

FIFO data register (SCFRDR) in asynchronous mode.

Bits 13 to 8 indicate the number of data with parity

errors after the ER bit in SCSSR is set.

If all 64-byte receive data in SCFRDR have parity

errors, bits PER5 to PER0 indicate 0s.

7, 6



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

FER5

FER4

FER3

FER2

FER1

FER0

Framing Error

Indicates the number of data, in which framing errors

are generated, in receive data stored in the receive

FIFO data register (SCFRDR) in asynchronous mode.

Bits 5 to 0 indicate the number of data with framing

errors after the ER bit in SCSSR is set.

If all 64-byte receive data in SCFRDR have framing

errors, bits FER5 to FER0 indicate 0s.

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