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SH7721 Datasheet(PDF) 662 Page - Renesas Technology Corp

Part # SH7721
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
PDF  1524 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7721 Datasheet(HTML) 662 Page - Renesas Technology Corp

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Section 18
Serial Communication Interface with FIFO (SCIF)
Rev. 3.00 Jan. 18, 2008 Page 600 of 1458
REJ09B0033-0300
18.3.8
Serial Status Register (SCSSR)
SCSSR is a 16-bit readable/writable register that indicates SCIF states. The ORER, TSF, ER,
TDFE, BRK, RDF, or DR flag cannot be set to 1. These flags can be cleared to 0 only if they have
first been read (after being set to 1). The flags TEND, FER, and PER are read-only bits and cannot
be modified.
Bit
Bit Name
Initial Value R/W
Description
15 to 10
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
9
ORER
0
R/(W)* Overrun Error Flag
Indicates that the overrun error occurred during
reception.
This bit is valid only in asynchronous mode.
0: Indicates during reception, or reception has been
completed without any error*
1
[Clearing conditions]
Power-on reset, manual reset
Writing 0 after reading ORER = 1
1: Indicates that the overrun error is generated during
reception*
2
[Setting condition]
When receive FIFO is full and the next serial data
reception is completed
Notes: 1. When the RE bit in SCSCR is cleared to 0,
the ORER flag is not affected and retains
its previous state.
2. SCFRDR holds the data received before
the overrun error, and newly received data
is lost. When ORER is set to 1,
subsequent serial data reception cannot
be carried out.



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