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SH7721 Datasheet(PDF) 665 Page - Renesas Technology Corp

Part # SH7721
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
PDF  1524 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7721 Datasheet(HTML) 665 Page - Renesas Technology Corp

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Section 18
Serial Communication Interface with FIFO (SCIF)
Rev. 3.00 Jan. 18, 2008 Page 603 of 1458
REJ09B0033-0300
Bit
Bit Name Initial Value
R/W
Description
4
BRK
0
R/(W)* Break Detection
Indicates that a break signal is detected in received
data in asynchronous mode.
0: No break signal is being received
[Clearing conditions]
• Power-on reset, manual reset
• BRK is read as 1, then written to with 0
1: A break signal is received *
[Setting conditions]
Data including a framing error is received
• A framing error with space 0 occurs in the
subsequent received data
Note:
*
When a break is detected, transfer of the
received data (H'00) to SCFRDR stops
after detection. When the break ends and
the receive signal becomes mark 1, the
transfer of the received data resumes.
3
FER
0
R
Framing Error
Indicates a framing error in the data read from the
receive FIFO data register (SCFRDR) in
asynchronous mode.
0: No framing error occurred in the data read from
SCFRDR
[Clearing conditions]
• Power-on reset, manual reset
• No framing error is present in the data read from
SCFRDR
1: A framing error occurred in the data read from
SCFRDR
[Setting condition]
• A framing error is present in the data read from
SCFRDR



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