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SH7721 Datasheet(PDF) 667 Page - Renesas Technology Corp

Part # SH7721
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
PDF  1524 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7721 Datasheet(HTML) 667 Page - Renesas Technology Corp

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Section 18
Serial Communication Interface with FIFO (SCIF)
Rev. 3.00 Jan. 18, 2008 Page 605 of 1458
REJ09B0033-0300
Bit
Bit Name Initial Value R/W
Description
1
RDF
0
R/(W)*
Receive FIFO Data Full
Indicates that received data is transferred to the
receive FIFO data register (SCFRDR), the number of
data in SCFRDR becomes more than the number of
receive triggers specified by the RTRG1 and RTRG0
bits in SCFCR.
0: The number of transmit data written to SCFRDR is
less than the specified number of receive triggers
[Clearing conditions]
• Power-on reset, manual reset
• SCFRDR is read until the number of receive data
in SCFRDR becomes less than the specified
number of receive triggers, and RDF is read as 1,
then written to with 0.
1: The number of receive data in SCFRDR is more
than the specified number of receive triggers
[Setting condition]
The number of receive data which is greater than the
specified number of receive triggers is being stored to
SCFRDR.*
Note:
*
Since SCFTDR is a 64-byte FIFO
register, the maximum number of data
which can be read when RDF is 1 is the
specified number of receive triggers. If
attempted to read after all data in
SCFRDR have been read, the data is
undefined. The number of receive data in
SCFRDR is indicated by the lower bits of
SCFTDR.



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