SH7721 datasheet(671/1524 Pages) RENESAS

671 / 1524 page

Section 18

Serial Communication Interface with FIFO (SCIF)

Rev. 3.00 Jan. 18, 2008 Page 609 of 1458

REJ09B0033-0300

18.3.10

FIFO Control Register (SCFCR)

SCFCR is a 16-bit readable/writable register that resets the number of data in the transmit and

receive FIFO registers, sets the number of trigger data, and contains an enable bit for the loop back

test.

Bit

Bit Name

Initial Value R/W

Description

TSE

R/W

Transmit Data Stop Enable

Enables or disables transmit data stop function. This

function is enabled only in asynchronous mode.

Since this function is not supported in synchronous

mode, clear this bit to 0 in synchronous mode.

0: Transmit data stop function disabled

1: Transmit data stop function enabled

TCRST

R/W

Transmit Count Reset

Clears the transmit count to 0. This bit is available

while the transmit data stop function is enabled.

0: Transmit count reset disabled*

1: Transmit count reset enabled (cleared to 0)

Note:

The transmit count is reset (cleared to 0)

by a power-on reset or manual reset.

13 to 11



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

RSTRG2

RSTRG1

RSTRG0

R/W

Trigger of the

RTS Output Active 2 to 0

The

RTS signal goes to high, when the number of

receive data count stored in the receive FIFO data

number of setting triggers listed below.

000: 63

001: 1

010: 8

011: 16

100: 32

101: 48

110: 54

111: 60

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