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SH7721 Datasheet(PDF) 674 Page - Renesas Technology Corp |
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SH7721 Datasheet(HTML) 674 Page - Renesas Technology Corp |
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674 / 1524 page  Section 18 Serial Communication Interface with FIFO (SCIF) Rev. 3.00 Jan. 18, 2008 Page 612 of 1458 REJ09B0033-0300 18.3.11 FIFO Data Count Register (SCFDR) SCFDR is a 16-bit register which indicates the number of data stored in the receive FIFO data register (SCFRDR). The SCFDR is always read from the CPU. The bits 14 to 8 of this register indicate the number of transmit data items stored in the SCFTDR that have not yet been transmitted. The bits 6 to 0 of this register indicate the number of receive data items stored in the SCFRDR. Bit Bit Name Initial Value R/W Description 15 — 0 R Reserved This bit is always read as 0. The write value should always be 0. 14 13 12 11 10 9 8 T6 T5 T4 T3 T2 T1 T0 0 0 0 0 0 0 0 R R R R R R R These bits indicate the number of non-transmitted data stored in the SCFTDR. The H'00 means no transmit data, and the H'40 means that the full of transmit data are stored in the SCFTDR. 7 — 0 R Reserved This bit is always read as 0. The write value should always be 0. 6 5 4 3 2 1 0 R6 R5 R4 R3 R2 R1 R0 0 0 0 0 0 0 0 R R R R R R R These bits indicate the number of receive data stored in the SCFRDR. The H'00 means no receive data, and the H'40 means that the full of receive data are stored in the SCFRDR. |
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