SH7721 datasheet(675/1524 Pages) RENESAS

675 / 1524 page

Section 18

Serial Communication Interface with FIFO (SCIF)

Rev. 3.00 Jan. 18, 2008 Page 613 of 1458

REJ09B0033-0300

18.3.12

Transmit Data Stop Register (SCTDSR)

SCTDSR is an 8-bit readable/writable register that sets the number of data to be transmitted. This

transmit operation stops after all data set by this register have been transmitted. Settable values are

H'00 (1 byte) to H'FF (256 bytes). The initial value of this register is H'FF.

18.4

Operation

For serial communication, the SCIF has asynchronous mode in which characters are synchronized

individually and synchronous mode in which synchronization is achieved with clock pulses. The

SCIF has the 64-byte FIFO buffer for both transmission and reception, reduces an overhead of the

CPU, and enables continuous high-speed communication.

18.4.1

Asynchronous Mode

Operation in asynchronous mode is described below.

The transmission and reception format is selected in the serial mode register (SCSMR), as listed in

table 18.2. The clock source of SCIF is determined by the combination of CKE1 and CKE0 bits in

the serial control register (SCSCR).

• Data length is selectable from seven or eight bits.

• Parity and multiprocessor bits are selectable. So is the stop bit length (one or two bits). The

combination of the preceding selections constitutes the communication format and character

length.

• In receiving, it is possible to detect framing errors, parity errors, overrun errors, receive FIFO

data full, receive data ready, and breaks.

• The number of stored data for both the transmit and receive FIFO registers is displayed.

• Clock source: Internal clock/external clock

 Internal clock: SCIF operates using the on-chip baud rate generator

 External clock: The clock appropriate for the sampling rate should be input. For example,

when the sampling rate is 1/16, input the clock frequency 8 times the bit rate. (The internal

baud rate generator should not be used.)

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