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SH7721 Datasheet(PDF) 679 Page - Renesas Technology Corp

Part # SH7721
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
PDF  1524 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7721 Datasheet(HTML) 679 Page - Renesas Technology Corp

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Section 18
Serial Communication Interface with FIFO (SCIF)
Rev. 3.00 Jan. 18, 2008 Page 617 of 1458
REJ09B0033-0300
(4)
Transmitting and Receiving Data (Serial data transmission)
Figure 18.3 shows a sample serial transmission flowchart. After SCIF transmission is enabled, use
the following procedure to perform serial data transmission.
Start transmission
Read TDFE bit in SCSSR
TEND= 1?
Read TEND bit in SCSSR2
Clear TE bit in SCSCR2 to 0
Set SCPDR2 and SCPCR2
Yes
No
TDFE= 1?
No
All data transmitted?
No
Yes
Yes
Break output?
Yes
No
Write transmit data (16 - transmit
trigger set number) to SCFTDR,
read 1 from TDFE bit and TEND flag
in SCSSR, then clear to 0
End of transmission
(1) SCIF status check and transmit data write:
Read serial status register (SCSSR) and
check that the TDFE flag is set to 1, then
write transmit data to the transmit FIFO
data register (SCFTDR), read 1 from the
TDFE and TEND flags, then clear these
flags to 0.
The number of transmit data bytes that can
be written is 64 - (transmit trigger set
number).
(2) Serial transmission continuation procedure:
To continue serial transmission, read 1 from
the TDFE flag to confirm that writing is
possible, then write data to SCFTDR2, and
then clear the TDFE flag to 0.
(3) Break output at the end of serial
transmission:
To output a break in serial transmission, set
the port SC data register (SCPDR) and port
SC control register (SCPCR), then clear the
TE bit to 0 in the serial control register
(SCSCR).
In steps 1 and 2, it is possible to ascertain
the number of data bytes that can be
written from the number of transmit data
bytes in SCFTDR indicated by the upper 8
bits of the FIFO data count set register 2
(SCFDR).
(1)
(2)
(3)
Figure 18.3
Sample Serial Transmission Flowchart



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