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SH7721 Datasheet(PDF) 683 Page - Renesas Technology Corp

Part # SH7721
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
PDF  1524 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7721 Datasheet(HTML) 683 Page - Renesas Technology Corp

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Section 18
Serial Communication Interface with FIFO (SCIF)
Rev. 3.00 Jan. 18, 2008 Page 621 of 1458
REJ09B0033-0300
(5)
Transmitting and Receiving Data (Serial data reception)
Figures 18.7 and 18.8 show sample serial reception flowcharts. After SCIF reception is enabled,
use the following procedure to perform serial data reception.
Start reception
Read PER and FER
flags in SCSSR
All data received?
End reception
No
Yes
PER or FER = 1?
RDF = 1?
Yes
Yes
Clear RE bit in SCSCR to 0
No
No
Read RDF flag in SCSSR
Error processing
Read receive data in SCFRDR,
and clear RDF flag in
SCSSR to 0
(1) Receive error handling and break
detection:
Read the DR, ER, and BRK flags in
SCSSR2 to identify any error, perform
the appropriate error handling, then
clear the DR, ER, and BRK flags to 0.
In the case of a framing error, a break
can also be detected by reading the
value of the RxD2 pin.
(2) SCIF status check and receive data
read :
Read the serial status register
(SCSSR) and check that RDF = 1, then
read the receive data in the receive
FIFO data register (SCFRDR), read 1
from the RDF flag, and then clear the
RDF flag to 0.
(3) Serial reception continuation
procedure:
To continue serial reception, read at
least the receive trigger set number of
receive data bytes from SCFRDR, read
1 from the RDF flag, then clear the
RDF flag to 0. The number of receive
data bytes in SCFRDR can be
ascertained by reading the lower bits of
SCFDR.
(1)
(2)
(3)
Figure 18.7
Sample Serial Reception Flowchart (1)



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