SH7721 datasheet(687/1524 Pages) RENESAS

687 / 1524 page

Section 18

Serial Communication Interface with FIFO (SCIF)

Rev. 3.00 Jan. 18, 2008 Page 625 of 1458

REJ09B0033-0300

When the external clock is selected:

The SCIF operates on the external clock input through the SCK pin.

18.4.4

Serial Operation in Synchronous Mode

don't care

LSB

MSB

Note: * High in continuous transmission/reception

Serial data

Serial clock

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

One unit of transfer data (character or frame)

Figure 18.12

Data Format in Synchronous Communication

In synchronous serial communication, data on the communication line is output from a falling

edge of the serial clock to the next falling edge. Data is guaranteed valid at the rising edge of the

serial clock.

In serial communication, each character is output starting with the LSB and ending with the MSB.

After the MSB is output, the communication line remains in the state of the MSB.

In synchronous mode, the SCIF receives data in synchronization with the rising edge of the serial

clock.

(1)

Data Transfer Format

A fixed 8-bit data format is used. No parity or multiprocessor bits are added.

(2)

Clock

An internal clock generated by the on-chip baud rate generator or an external clock input through

the SCK pin can be selected as the serial clock for the SCIF, according to the setting of the CKE1

and CKE0 bits in SCSCR.

Eight serial clock pulses are output in the transfer of one character, and when no

transmission/reception is performed, the clock is fixed high. However, when the operation mode is

reception only, the synchronous clock output continues while the RE bit is set to 1. To fix the

clock high every time one character is transferred, write to the transmit FIFO data register

(SCFTDR) the same number of dummy data bytes as the data bytes to be received and set the TE

and RE bits to 1 at the same time to transmit the dummy data. When the specified number of data

bytes are transmitted, the clock is fixed high.

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