SH7721 datasheet(684/1524 Pages) RENESAS

684 / 1524 page

Section 18

Serial Communication Interface with FIFO (SCIF)

Rev. 3.00 Jan. 18, 2008 Page 622 of 1458

REJ09B0033-0300

Error processing

End

BRK= 1?

DR= 1?

ER = 1?

Yes

Clear DR, ER, BRK flags in

SCSSR to 0

Receive error processing

Break processing

Read receive data in SCFRDR

1. Whether a framing error or parity error has

occurred in the receive data read from

SCFRDR can be ascertained from the FER and

PER bits in SCSSR.

2. When a break signal is received, receive data

is not transferred to SCFRDR while the BRK

flag is set. However, note that the last data in

SCFRDR is H'00 and the break data in which a

framing error occurred is stored.

Figure 18.8

Sample Serial Reception Flowchart (2)

In serial reception, the SCIF operates as described below.

1. The SCIF monitors the transmission line, and if a 0 start bit is detected, performs internal

synchronization and starts reception.

The received data is stored in SCRSR in LSB-to-MSB order.

3. The parity bit and stop bit are received.

After receiving these bits, the SCIF carries out the following checks.

A. Stop bit check: The SCIF checks whether the stop bit is 1. If there are two stop bits, only

the first is checked.

B. The SCIF checks whether receive data can be transferred from the receive shift register

(SCRSR) to SCFRDR.

C. Break check: The SCIF checks that the BRK flag is 0, indicating that the break state is not

set.

SH7721 Datasheet(PDF) 684 Page - Renesas Technology Corp