SH7721 datasheet(688/1524 Pages) RENESAS

688 / 1524 page

Section 18

Serial Communication Interface with FIFO (SCIF)

Rev. 3.00 Jan. 18, 2008 Page 626 of 1458

REJ09B0033-0300

(3)

Data Transfer Operations (SCIF Initialization)

Before transmitting and receiving data, it is necessary to clear the TE and RE bits in SCSCR to 0,

then initialize the SCIF as described below.

When the clock source, etc., is changed, the TE and RE bits must be cleared to 0 before making

the change using the following procedure. When the TE bit is cleared to 0, the transmit shift

contents of SCSSR, SCFTDR, or SCFRDR. The TE bit should be cleared to 0 after all transmit

data has been sent and the TEND bit in SCSSR has been set to 1. The TE bit should not be cleared

to 0 during transmission; if attempted, the TxD pin will go to the high-impedance state. Before

setting TE to 1 again to start transmission, the TFRST bit in SCFCR should first be set to 1 to reset

SCFTDR.

Figure 18.13 shows sample SCIF initialization flowcharts.

Yes

Wait

End

1-bit interval elapsed?

Set transmit trigger number in TTRG1

and TTRG0 in SCFCR, write transmit

data exceeding transmit trigger setting

number, and clear TDFE flag to 0 after

reading 1 from it

Initialization

Clear TE and RE bits in SCSCR to 0

Set TFRST bit in SCFCR to 1

Set CKE1 and CKE0 bits in SCSCR

(leaving TE and RE bits cleared to 0)

Set C/A bit in SCSMR to 1

Set CKS1 and CKS0 bits

Set value in SCBRR

Clear TFRST bit to 0

1. Be sure to set the TFRST bit in

SCFCR to 1, to reset the FIFOs.

2. Set the clock selection in SCSCR.

Be sure to clear bits RIE, TIE, TE,

and RE to 0.

3. Set the clock source selection in

SCSMR.

4. Write a value corresponding to the

bit rate into SCBRR.

5. Clear the TFRST bit in SCFCR to 0.

6. Set the transmit trigger number,

write transmit data exceeding the

transmit trigger setting number, and

clear the TDFE flag to 0 after reading

it.

7. Wait one bit interval.

Figure 18.13

Sample SCIF Initialization Flowchart (1) (Transmission)

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