SH7721 datasheet(685/1524 Pages) RENESAS

685 / 1524 page

Section 18

Serial Communication Interface with FIFO (SCIF)

Rev. 3.00 Jan. 18, 2008 Page 623 of 1458

REJ09B0033-0300

If all the above checks are passed, the receive data is stored in SCFRDR.

Note:

Even when the receive error (framing error/parity error) is generated, receive operation is

continued.

4. If the RIE bit in SCSCR is set to 1 when the RDF flag changes to 1, a receive-FIFO-data-full

interrupt request is generated.

If the ERIE bit in SCSCR is set to 1 when the ER flag changes to 1, a receive-error interrupt

request is generated.

If the BRIE bit in SCSCR is set to 1 when the BRK flag changes to 1, a break reception

interrupt request is generated.

If the DRIE bit in SCSCR is set to 1 when the DR flag changes to 1, a receive data ready

interrupt request is generated.

Note that a common vector is assigned to each interrupt source.

Figure 18.9 shows an example of the operation for reception.

RDF

FER

Receive-error interrupt

request generated

by receive error

One frame

Data read and RDF

flag read as 1 then

cleared to 0 by

receive-FIFO-data-ful

interrupt handler

Receive-FIFO-data-full

interrupt request

0/1

Parity

bit

Parity

bit

Serial

data

Start

bit

Data

Stop

bit

Start

bit

Data

Stop

bit

Idle state

(mark state)

D0 D1

D7 0/1

Figure 18.9

Example of SCIF Receive Operation

(Example with 8-Bit Data, Parity, One Stop Bit)

When modem control is enabled, transmission can be stopped and restarted in accordance with the

CTS input value. When CTS is set to 1, if transmission is in progress, the line goes to the mark

state after transmission of one frame. When

CTS is set to 0, the next transmit data is output

starting from the start bit.

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