SH7721 datasheet(681/1524 Pages) RENESAS

Part #	SH7721

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

PDF	1524 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

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Section 18

Serial Communication Interface with FIFO (SCIF)

Rev. 3.00 Jan. 18, 2008 Page 619 of 1458

REJ09B0033-0300

Figure 18.4 shows an example of the operation for transmission in asynchronous mode.

0/1

TDFE

TEND

Parity

bit

Parity

bit

Serial

data

Start

bit

Data

Stop

bit

Start

bit

Data

Stop

bit

Idle

state

(mark state)

Transmit-FIFO-

data-empty

interrupt request

Data written to

SCFTDR and TDFE

flag read as 1 then

cleared to 0 by Transmit-

FIFO-data-empty

interrupt handler

One frame

0/1

Transmit-FIFO-

data-empty

interrupt request

Figure 18.4

Example of Transmit Operation

(Example with 8-Bit Data, Parity, One Stop Bit)

• Transmit data stop function

When the value of the SCTDSR register and the number of transmit data match, transmit

operation stops. Setting the TSIE bit (interrupt enable bit) allows the generation of an interrupt

and activation of DMAC.

Figure 18.5 shows an example of the operation for transmit data stop function.

TSF flag

0/1

Start

bit

Transmit data

TxD

Parity

bit

Stop

bit

Start

bit

Figure 18.5

Example of Transmit Data Stop Function

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