SH7721 datasheet(677/1524 Pages) RENESAS

677 / 1524 page

Section 18

Serial Communication Interface with FIFO (SCIF)

Rev. 3.00 Jan. 18, 2008 Page 615 of 1458

REJ09B0033-0300

Table 18.3

Serial Transmit/Receive Formats

SCSMR Bits

Serial Transmit/Receive Format and Frame Length

CHR PE

STOP

START

8-Bit data

STOP

START

8-Bit data

STOP STOP

START

8-Bit data

STOP

START

8-Bit data

STOP STOP

START

7-Bit data

STOP

START

7-Bit data

STOP STOP

START

7-Bit data

STOP

START

7-Bit data

STOP STOP

(2)

Clock

Either an internal clock generated by the on-chip baud rate generator or an external clock input at

the SCK pin can be selected as the SCI's serial clock, according to the setting of the CKE bit in the

serial control register (SCSCR).

When an external clock is input at the SCK pin, the clock appropriate for the sampling rate should

be input. For example, when the sampling rate is 1/16, the clock frequency should be 8 times the

bit rate used.

(3)

Transmitting and Receiving Data (SCIF Initialization)

Before transmitting or receiving, clear the TE and RE bits to 0 in SCSCR, then initialize the SCIF

as follows.

When changing the communication format, always clear the TE and RE bits to 0 before following

the procedure given below. Clearing TE to 0 initializes the transmit shift register (SCTSR).

Clearing TE and RE to 0, however, does not initialize the serial status register (SCSSR), transmit

FIFO data register (SCFTDR), or receive FIFO data register (SCFRDR), which retain their

previous contents.

Clear TE to 0 after all transmit data are transmitted and the TEND bit in the SCSSR is set. The

transmitting data enters the high impedance state after clearing to 0 although the bit can be cleared

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