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SH7721 Datasheet(PDF) 673 Page - Renesas Technology Corp |
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SH7721 Datasheet(HTML) 673 Page - Renesas Technology Corp |
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673 / 1524 page  Section 18 Serial Communication Interface with FIFO (SCIF) Rev. 3.00 Jan. 18, 2008 Page 611 of 1458 REJ09B0033-0300 Bit Bit Name Initial Value R/W Description 2 TFRST 0 R/W Transmit FIFO Data Register Reset Cancels the transmit data in the transmit FIFO data register and resets the data to the empty state. 0: Disables reset operation* 1: Enables reset operation Note: * The reset is executed in a power-on reset or a manual reset. 1 RFRST 0 R/W Receive FIFO Data Register Reset Cancels the receive data in the receive FIFO data register and resets the data to the empty state. 0: Disables reset operation* 1: Enables reset operation Note: * The reset is executed in a power-on reset or a manual reset. 0 LOOP 0 R/W Loop Back Test Internally connects the transmit output pin (TxD) and receive input pin (RxD) and enables the loop back test. 0: Disables the loop back test 1: Enables the loop back test |
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