SH7721 datasheet(686/1524 Pages) RENESAS

686 / 1524 page

Section 18

Serial Communication Interface with FIFO (SCIF)

Rev. 3.00 Jan. 18, 2008 Page 624 of 1458

REJ09B0033-0300

Figure 18.10 shows an example of the operation when modem control is used.

CTS

Transmission stops

when

CTS goes high

Transmission starts again

when

CTS goes low

0/1

Start

bit

Transmit data

TxD

Parity

bit

Stop

bit

Start

bit

Figure 18.10

Example of

CTS Control Operation

When modem control is enabled, the

RTS signal goes high after the number of receive FIFO

(SCFRDR) has exceeded the number of

RTS output triggers.

RTS

RTS goes high when receive data is

at least number of

RTS output trigger

0D0

0/1

Start

bit

Transmit data

TxD

Parity

bit

Stop

bit

RTS goes low when receive data is

less than number of

RTS output trigger

Figure 18.11

Example of

RTS Control Operation

18.4.3

Synchronous Mode

Operation in synchronous mode is described below.

The SCIF has 64-stage FIFO buffers for both transmission and reception, reducing the CPU

overhead and enabling fast, continuous communication to be performed.

The operating clock source is selected using the serial mode register (SCSMR). The SCIF clock

source is determined by the CKE1 and CKE0 bits in the serial control register (SCSCR).

• Transmit/receive format: Fixed 8-bit data

• Indication of the number of data bytes stored in the transmit and receive FIFO registers

• Internal clock or external clock used as the SCIF clock source

When the internal clock is selected:

The SCIF operates on the baud rate generator clock and outputs a serial clock from SCK pin.

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