SH7721 datasheet(668/1524 Pages) RENESAS

Part #	SH7721

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

PDF	1524 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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668 / 1524 page

Section 18

Serial Communication Interface with FIFO (SCIF)

Rev. 3.00 Jan. 18, 2008 Page 606 of 1458

REJ09B0033-0300

Bit

Bit Name

Initial Value

R/W

Description

R/(W)*

Receive Data Ready

Indicates that the receive FIFO data register

(SCFRDR) stores the data which is less than the

specified number of receive triggers, and that next

data is not yet received after 15 etu has elapsed

from the last stop bit in asynchronous mode.

0: Receive is in progress, or no received data

remains in SCFRDR after the receive ended

normally.

[Clearing conditions] (Initial value)

• Power-on reset, manual reset

• All receive data in SCFRDR is read, and DR is

read as 1, then written to with 0.

1: Next receive data is not received

[Setting condition]

SCFRDR stores the data which is less than the

specified number of receive triggers, and that next

data is not yet received after 15 etu has elapsed

from the last stop bit.*

Note:

This is equivalent to 1.5 frames with the

8-bit 1-stop-bit format. (etu: Element

Time Unit)

Note:

The only value that can be written is 0 to clear the flag.

SH7721 Datasheet(PDF) 668 Page - Renesas Technology Corp