SH7721 datasheet(660/1524 Pages) RENESAS

660 / 1524 page

Section 18

Serial Communication Interface with FIFO (SCIF)

Rev. 3.00 Jan. 18, 2008 Page 598 of 1458

REJ09B0033-0300

Bit

Bit Name Initial Value R/W Description

R/W Receive Enable

Enables or disables the SCIF serial receiver.

0: Receiver disabled*

1: Receiver enabled*

Notes: 1. Clearing RE to 0 does not affect the receive

flags (DR, ER, BRK, RDF, FER, PER, and

ORER). These flags retain their previous

values.

2. The serial mode register (SCSMR) and FIFO

control register (SCFCR) should be set to

select the receive format and reset the receive

FIFO before setting the RE bit to 1.

3, 2

—

All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

CKE1

CKE0

R/W

Clock Enable 1and 0

These bits select the SCIF clock source. The bits CKE1

and CKE0 should be set before selecting the SCIF

operating mode by SCSMR.

00: Internal clock, SCK pin used for input pin (input signal

is ignored)*

01: Internal clock, SCK pin used for synchronous clock

output*

10: External clock, SCK pin used for clock input*

11: External clock, SCK pin used for clock input*

Notes: 1. When the data sampling is executed using on-

chip baud rate generator, CKE1 and CKE0

should be set to 00.

2. In synchronous mode, a clock with a

frequency equal to the bit rate is output. When

the channel 0 is used as the IrDA interface,

CKE1 and CKE0 should be set to 01.

3. In asynchronous mode, input the clock which

is appropriate for the sampling rate. For

example, when the sampling rate is 1/16,

input the clock frequency 8 times the bit rate.

When the external clock is not input, CKE1

and CKE0 should be set to 00.

When the SCK pin is set as an I/O port pin,

CKE1 and CKE0 should be set to 00.

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