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SH7721 Datasheet(PDF) 1071 Page - Renesas Technology Corp |
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SH7721 Datasheet(HTML) 1071 Page - Renesas Technology Corp |
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1071 / 1524 page  Section 30 SIM Card Module (SIM) Rev. 3.00 Jan. 18, 2008 Page 1009 of 1458 REJ09B0033-0300 Table 30.2 Register Settings for Smart Card Interface Bit Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SCSMR 0 0 PE O/ E 0 0 0 0 SCBRR 0 0 0 0 0 BRR2 BRR1 BRR0 SCSCR TIE RIE TE RE WAIT_IE TEIE CKE1 CKE0 SCTDR SCTD7 SCTD6 SCTD5 SCTD4 SCTD3 SCTD2 SCTD1 SCTD0 SCSSR TDRE RDRF ORER ERS PER TEND WAIT_ER 0 SCRDR SCRD7 SCRD6 SCRD5 SCRD4 SCRD3 SCRD2 SCRD1 SCRD0 SCSCMR 0 LCB PB 0 SDIR SINV RST 1 SCSC2R EIO 0 0 0 0 0 0 0 SCWAIT SCWAIT15 to SCWAIT0 SCGRD SCGRD7 to SCGRD0 SCSMPL SCSMPL10 to SCSMPL0, bits 11 to 15 are 0 • Serial mode register (SCSMR) setting When the IC card is set for the direct convention, the O/ E bit is cleared to 0; for the inverse convention, it is set to 1. • Bit rate register (SCBRR) setting Sets the bit rate. For the method of computing settings, refer to section 30.4.4, Clocks. • Serial control register (SCSCR) settings Each interrupt can be enabled and disabled using the TIE, RIE, TEIE, and WAIT_IE bits. By setting either the TE or RE bit to 1, transmission or reception is selected. The CKE1 and CKE0 bits are used to select the clock output state. For details, refer to section 30.4.4, Clocks. • Smart card mode register (SCSCMR) settings When the IC card is set for the direct convention, both the SDIR and SINV bits are cleared to 0; for the inverse convention, both are set to 1. The SMIF bit is always set to 1. Figure 30.3 below shows the register settings and waveform examples at the start character for two types of IC cards (a direct-convention type and an inverse-convention type). For the direct-convention type, the logical level 1 is assigned to the Z state, and the logical level 0 to the A state, and transmission and reception are performed in LSB-first. The data of the above start character is then H'3B. Even parity is used according to the smart card specification, and so the parity bit is 1. |
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