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SH7721 Datasheet(PDF) 1072 Page - Renesas Technology Corp

Part # SH7721
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
PDF  1524 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7721 Datasheet(HTML) 1072 Page - Renesas Technology Corp

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Section 30
SIM Card Module (SIM)
Rev. 3.00 Jan. 18, 2008 Page 1010 of 1458
REJ09B0033-0300
For the inverse-convention type, the logical level 1 is assigned to the A state, and the logical
level 0 to the Z state, and transmission and reception are performed in MSB-first. The data of
the start character shown in figure 30.3 is then H'3F. Even parity is used according to the smart
card specification, and so the parity bit is 0 corresponding to the Z state.
In addition, the only D7 to D0 bits are inverted by the SINV bit. The O/
E bit in SCSMR is set to
odd parity mode to invert the parity bit. In transmission and reception, the setting condition is
similar.
Ds
D0
D1
D2
D3
D4
D5
D6
D7
Dp
Ds
D7
D6
D5
D4
D3
D2
D1
D0
Dp
A
ZZ
A
ZZ
A
AZ
Z
A
ZZ
A
AA
A
AZ
A
(Z)
(Z)
(Z)
(Z)
state
state
(a) Direct convention (SDIR=SINV=O/
E=0)
(b) Inverse convention (SDIR=SINV=O/
E=1)
Figure 30.3
Examples of Start Character Waveforms



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