SH7721 datasheet(1115/1524 Pages) RENESAS

1115 / 1524 page

Section 31

MultiMediaCard Interface (MMCIF)

Rev. 3.00 Jan. 18, 2008 Page 1053 of 1458

REJ09B0033-0300

31.3.15

Transfer Clock Control Register (CLKON)

CLKON controls the transfer clock frequency and clock on/off.

The 33-MHz peripheral clock is needed, and bits CSEL3 to CSEL0 should be set to 0001 for a

16.5-Mbps transfer clock of the MMCIF. At this time, transfer should be performed by sufficiently

slow transfer clock in the open drain state.

In the command sequence, do not perform clock on/off or frequency modification.

Bit

Bit Name

Initial

Value

R/W

Description

CLKON

R/W

Clock On

0: Stops the transfer clock output from the CLK/SCLK

pin.

1: Outputs the transfer clock from the CLK/SCLK pin.

6 to 4

—

All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

CSEL3

CSEL2

CSEL1

CSEL0

R/W

Transfer Clock Frequency Select

0000: Setting prohibited

0001: Uses the 1/2-divided peripheral clock as a transfer

clock.

0010: Uses the 1/4-divided peripheral clock as a transfer

clock.

0011: Uses the 1/8-divided peripheral clock as a transfer

clock.

0100: Uses the 1/16-divided peripheral clock as a

transfer clock.

0101: Uses the 1/32-divided peripheral clock as a

transfer clock.

0110: Uses the 1/64-divided peripheral clock as a

transfer clock.

0111: Uses the 1/128-divided peripheral clock as a

transfer clock.

1000: Uses the 1/256-divided peripheral clock as a

transfer clock.

1001 to 1111: Setting prohibited

Note:

The maximum operating frequency of the peripheral clock is 33.34 MHz.

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