SH7721 datasheet(1118/1524 Pages) RENESAS

Part #	SH7721

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

PDF	1524 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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1118 / 1524 page

Section 31

MultiMediaCard Interface (MMCIF)

Rev. 3.00 Jan. 18, 2008 Page 1056 of 1458

REJ09B0033-0300

Bit

Bit Name

Initial

Value

R/W

Description

SET2

SET1

SET0

R/W

Sets DMA request signal assert condition.

000: Not output (Initial value)

001: FIFO remained data is 1/4 or less of FIFO capacity.

010: FIFO remained data is 1/2 or less of FIFO capacity.

011: FIFO remained data is 3/4 or less of FIFO capacity.

100: FIFO remained data is at least 1 byte.

101: FIFO remained data is 1/4 or more of FIFO capacity.

110: FIFO remained data is 1/2 or more of FIFO capacity.

111: FIFO remained data is 3/4 or more of FIFO capacity.

31.3.20

Interrupt Control Register 2 (INTCR2)

The INTCR2 enables or disables an interrupt.

Bit

Bit Name

Initial

Value

R/W

Description

INTRQ3E

R/W

int_frdy_nb Interrupt Enable

0: Interrupt disabled

1: Interrupt enabled

6 to 1



All 0



Reserved

These bits are always read as 0. The write value should

always be 0.

FRDYIE

R/W

FIFO Preparation End Flag Enable

0: Disables FIFO preparation end flag set

1: Enables FIFO preparation end flag set

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