SH7721 datasheet(1116/1524 Pages) RENESAS

Part #	SH7721

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

PDF	1524 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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1116 / 1524 page

Section 31

MultiMediaCard Interface (MMCIF)

Rev. 3.00 Jan. 18, 2008 Page 1054 of 1458

REJ09B0033-0300

31.3.16

VDD/Open-Drain Control Register (VDCNT)

VDCNT can use

MMC_ODMOD signal to control open drain. The MMC_VDDON signal output

can be used to control the MMC power supply (VDD) on/off.

Bit

Bit Name

Initial

Value

R/W

Description

VDDON

R/W

Specifies MMC_VDDON signal to be used as a MMC

power supply (VDD) control signal.

0: MMC_VDDON is low signal output

1: MMC_VDDON is high signal output

ODMOD

R/W

Specifies

MMC_ODMOD signal to be used to control

CMD output open drain in MMC mode.

MMC_ODMOD signal is low signal output

MMC_ODMOD signal is high signal output

5 to 0



All 0



Reserved

These bits are always read as 0. The write value should

always be 0.

31.3.17

Data Register (DR)

DR is a register for reading/writing FIFO data.

Word/byte access is enabled to addresses of this register.

Bit

Bit Name

Initial

Value

R/W

Description

15 to 0

(7 to 0)

Undefined

R/W

Word/byte access is enabled. However, byte access is

disabled to address 2n+1.

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