SH7721 datasheet(1119/1524 Pages) RENESAS

Part #	SH7721

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

PDF	1524 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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1119 / 1524 page

Section 31

MultiMediaCard Interface (MMCIF)

Rev. 3.00 Jan. 18, 2008 Page 1057 of 1458

REJ09B0033-0300

31.3.21

Interrupt Status Register 2 (INTSTR2)

The INTSTR2 controls the MMCIF interrupt output.

If setting condition is satisfied, FRDYI is set even though it has been cleared. Disable flag setting

by FRDYIE in INTCR2 before clearing FRDYI.

Bit

Bit Name

Initial

Value

R/W

Description

7 to 2



All 0



Reserved

These bits are always read as 0. The write value should

always be 0.

FRDY_TU 1

When FRDYI setting condition is satisfied.

Read value

0: When FIFO remained data is less than data set as

assert condition by DMACR

1: When FIFO remained data is other than data set as

assert condition by DMACR

FRDYIE

R/(W)* FIFO Preparation End Flag Enable

[Setting condition]

When FIFO remained data is less than data set as assert

condition by DMACR while FRDYIE = 1 and the DMAEN

bit is set.

[Clearing condition]

Write 0 after reading FRDYI = 1.

Note:

Cleared by writing 0 after reading 1.

SH7721 Datasheet(PDF) 1119 Page - Renesas Technology Corp