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7721 Datasheet(PDF) 355 Page - Renesas Technology Corp

Part # 7721
Description  16-BIT SINGLE-CHIP MICROCOMPUTER
PDF  577 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

7721 Datasheet(HTML) 355 Page - Renesas Technology Corp

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DMA CONTROLLER
13-76
13.7 Array chain transfer mode
7721 Group User’s Manual
Fig. 13.7.6 Operation flowchart of array chain transfer mode
Burst·Level·H
Cycle-steal·No request
Note: When TC pin validity bit is “1”
First of 1 block ?
SARi
← Transfer parameter (Note)
(Transfer source’s transfer start address)
DARi
← Transfer parameter (Note)
(Transfer destination’s transfer start address)
TCRi
← Transfer parameter
(Byte number of transfer data)
TCRi latch
← TCRi latch – 1
N
Y
1
0
First
On and after
second
Transfer
completion of all blocks ?
TCRi latch = 0 ?
Y. Completion
1
N
DMAi request bit
← 0
1-unit transfer
Transfer completion
of 1 block ?
(Only in cycle-steal transfer mode)
(Refer to section “13.4 Operation.”)
TC “L” output (Note)
DMAi interrupt request bit
← 1
DMAi enable bit
← 0
DMAi request bit
← 0
(Only in burst transfer mode (edge sense))
DMAi request bit ?
Burst·Level·H
Cycle-steal·No request
0
Burst·Edge
: In burst transfer mode (edge sense)
Burst·Level·L
: In burst transfer mode (level sense) with DMAREQi pin = L
Burst·Level·H
: In burst transfer mode (level sense) with DMAREQi pin = H
Cycle-steal·Requested
: In cycle-steal transfer mode with any request of DMA0–3
Cycle-steal·No request
: In cycle-steal transfer mode with no request of DMA0–3
SARi latch indicates the start address of the transfer parameter memory of the next block.
TCRi latch indicates the number of remaining transfer blocks.
Note: The above figure applies when 2-bus cycle transfer is performed.
When data is transferred from memory to I/O in 1-bus cycle transfer, there is no “DARi
← Transfer parameter.”
When data is transferred from I/O to memory in 1-bus cycle transfer, there is no “SARi
← Transfer parameter.”
Burst•Edge
Burst·Level·L
Cycle-steal·Requested
DMAi request bit ?
Burst·Edge
Burst·Level·L
Cycle-steal·Requested



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