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7721 Datasheet(PDF) 71 Page - Renesas Technology Corp |
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7721 Datasheet(HTML) 71 Page - Renesas Technology Corp |
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71 / 577 page  RESET 7721 Group User’s Manual 4–8 4.1 Hardware reset UART1 receive interrupt control register 6016 6116 6216 6316 6416 6516 6616 6716 6816 6916 7016 7116 7216 7316 7416 7516 7616 7716 7816 7916 7A16 7B16 7C16 7D16 7E16 7F16 6B16 6C16 6D16 6E16 6F16 6A16 Address A-D conversion interrupt control register UART0 transmit interrupt control register UART1 transmit interrupt control register INT2 interrupt control register Watchdog timer frequency select register Register name Watchdog timer register Timer A0 interrupt control register Timer A2 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register Timer B1 interrupt control register Timer B2 interrupt control register INT0 interrupt control register Access characteristics RW b7 b0 RW State immediately after reset 0 ?(Note 6) b7 b0 UART0 receive interrupt control register Timer A1 interrupt control register Timer B0 interrupt control register INT1 interrupt control register 0 0 00 0 By writing dummy data to address 6016, the value “FFF16” is set to the watchdog timer. The dummy data is not retained anywhere. The value “FFF16” is set to the watchdog timer. (Refer to “CHAPTER 15. WATCHDOG TIMER.”) It is possible to read the bit state at reading. When writing “0” to this bit, this bit becomes “0.” But when writing “1” to this bit, this bit does not change. RW Notes 5: 6: 7: (Note 5) ? ? ? RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 0 00 0 ? 0 00 0 ? 0 00 0 ? 0 00 0 ? 0 00 0 ? 0 00 0 ? 0 00 0 ? 0 00 0 ? 0 00 0 ? 0 00 0 ? 0 00 0 ? 0 00 0 0 00 0 0 00 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? ? 0 00 Real-time output control register Refresh timer DM AC control register L DM AC control register H DM A0 interrupt control register DM A1 interrupt control register DM A2 interrupt control register DM A3 interrupt control register RW 0 0 0 0 0 0 0 0 RW RW DRAM control register WO RW (Note 7) RW WO RW RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ?? 0 0 00 0 ? ? 0 00 0 ? 0 00 0 ? 0 00 Fig. 4.1.7 State of SFR and internal RAM areas immediately after reset (4) |
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