7721 datasheet(31/577 Pages) RENESAS

31 / 577 page

CENTRAL PROCESSING UNIT (CPU)

2.1 Central processing unit

2–8

7721 Group User’s Manual

(6)

Bit 5: Data length flag (m)

It determines whether to use a data as a 16-bit unit or as an 8-bit unit. A data is treated as a 16-

bit unit when this flag is “0,” and as an 8-bit unit when it is “1.”

Use the SEM or SEP instruction to set this flag to “1,” and use the CLM or CLP instruction to clear

it to “0.” This flag is cleared to “0” at reset.

Note: When transferring data between registers which are different in bit length, the data is transferred

with the length of the destination register, but except for the TXA, TYA, TXB, TYB, and TXS

instructions. Refer to “7700 Family Software Manual” for details.

(7)

Bit 6: Overflow flag (V)

It is used when adding or subtracting with a word regarded as signed binary. When the data length

flag (m) is “0,” the overflow flag is set to “1” when the result of addition or subtraction exceeds the

range between –32768 and +32767, and cleared to “0” in all other cases. When the data length flag

(m) is “1,” the overflow flag is set to “1” when the result of addition or subtraction exceeds the range

between –128 and +127, and cleared to “0” in all other cases.

The overflow flag is also set to “1” when a result of division exceeds the register length to be stored

in a division instruction DIV.

When the BVC or BVS instruction is executed, this flag’s contents determine whether the program

causes a branch or not.

Use the SEP instruction to set this flag to “1,” and use the CLV or CLP instruction to clear it to “0.”

Note: This flag is invalid in the decimal mode.

(8)

Bit 7: Negative flag (N)

It is set to “1” when a result of arithmetic operation or data transfer is negative. (Bit 15 of the result

is “1” when the data length flag (m) is “0,” or bit 7 of the result is “1” when the data length flag (m)

is “1.”) It is cleared to “0” in all other cases. When the BPL or BMI instruction is executed, this flag

determines whether the program causes a branch or not. Use the SEP instruction to set this flag to

“1,” and use the CLP instruction to clear it to “0.”

Note: This flag is invalid in the decimal mode.

(9)

Bits 10 to 8: Processor interrupt priority level (IPL)

These three bits can determine the processor interrupt priority level to one of levels 0 to 7. The

interrupt is enabled when the interrupt priority level of a required interrupt, which is set in each

interrupt control register, is higher than IPL. When an interrupt request is accepted, IPL is stored in

the stack area, and IPL is replaced by the interrupt priority level of the accepted interrupt request.

There are no instruction to directly set or clear the bits of IPL. IPL can be changed by storing the

new IPL into the stack area and updating the processor status register with the PUL or PLP instruction.

The contents of IPL is cleared to “0002” at reset.

7721 Datasheet(PDF) 31 Page - Renesas Technology Corp

7721 Datasheet(HTML) 31 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL