7721 datasheet(86/577 Pages) RENESAS

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CLOCK GENERATING CIRCUIT

7721 Group User’s Manual

5–9

5.4 Wait mode

Wait mode is used to stop

φCPU and φ when there is no need to operate the central processing unit (CPU).

The microcomputer enters Wait mode when the WIT instruction is executed.

Wait mode can be terminated by an interrupt request occurrence or the hardware reset.

5.4.1 Wait mode

When the WIT instruction is executed,

φCPU and φ stop. The oscillator’s oscillation is not stopped. This state

is called “Wait mode.”

In Wait mode, the microcomputer’s power consumption is lowered though Vcc (power source voltage) is

maintained.

Table 5.4.1 lists the microcomputer’s state and operation in and after Wait mode.

Table 5.4.1 Microcomputer’s state and operation in and after Wait mode

5.4 Wait mode

State and Operation

Item

Oscillation

φCPU, φ

Clock

φ1, f2 to f512

Timer A

Timer B

Serial I/O

A-D converter

DMA controller

DRAM controller

Watchdog timer

Pins

State in

Wait mode

Operation after

terminating

Wait mode

By interrupt request occurrence

By hardware reset

Operating

Stopped

Operating

Stopped

Stopped (Note)

Operating

Retains the same state in which the WIT instruction was executed

Supply of

φCPU and φ starts just after the termination.

Operates in the same way as hardware reset.

Note: The refresh timer operates, but DRAM refresh is not performed because the bus request (DRAMC)

does not occur. (Refer to section “Appendix 9. 7721 Group Q & A.”)

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