7721 datasheet(51/577 Pages) RENESAS

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CONNECTION WITH EXTERNAL DEVICES

3.1 Signals required for accessing external devices

7721 Group User’s Manual

3–4

(5)

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Byte low enable signal (BLE), Byte high enable signal (BHE)

____

The BLE signal indicates the access to an even address. This signal becomes “L” level when

accessing only an even address or when simultaneously accessing both an even and an odd address.

____

The BHE signal indicates the access to an odd address. This signal becomes “L” level when accessing

only an odd address or when simultaneously accessing both an odd and an even address.

These signals are used to connect memories or I/O devices of which data bus width is 8 bits when

____

the external data bus width is 16 bits. Table 3.1.2 lists levels of the BLE and BHE signals and access

addresses.

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Table 3.1.2 Levels of BLE and BHE signals and access addresses

Even and odd addresses

(Simultaneous 2-byte access)

Even address

(1-byte access)

Odd address

(1-byte access)

Access address

____

BLE

____

BHE

(6)

Address latch enable signal (ALE)

This signal is used to latch the address from the multiplexed signal, which consists of the address

and data. (This multiplexed signal is input to or output from the A8/D8–A15/D15 and A16/D0–A23/D7 pins.)

When the ALE signal is “H,” latch the address and simultaneously output the addresses. When this

signal is “L,” retain the latched address.

(7)

____

Ready function-related signal (RDY)

This is the signal to use Ready function (Refer to section “3.3 Ready function.”)

(8)

_____

Hold function-related signal (HOLD)

This is the signal to use Hold function. (Refer to section “3.4 Hold function.”)

(9)

Status signals (ST0, ST1)

These signals indicate the bus use status. Table 3.1.3 lists the bus use status indicated by the ST0

and ST1 signals.

(10) Clock

φ1

This signal has the same period as

φ.

Table 3.1.3 Bus use status indicated by ST0 and

ST1 signals

Bus use status

DRAM refresh

Hold

DMA

CPU

ST1

ST0

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