7721 datasheet(20/577 Pages) RENESAS

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DESCRIPTION

7721 Group User’s Manual

1–5

Table 1.3.2 Pin description (2)

1.3 Pin description

Functions

Low-order 8 bits (A0–A7) of the address are output.

When the DRAM is accessed, the row and column

addresses are output with the time-sharing.

qExternal data bus width = 8 bits (When the BYTE

pin is “H” level)

Middle-order 8 bits (A8–A15) of the address are output.

qExternal data bus width = 16 bits (When the BYTE

pin is “L” level)

Data (D8–D15) input/output and output of the middle-

order 8 bits (A8–A15) of the address are performed

with the time-sharing.

Data (D0–D7) input/output and output of the high-order

8 bits (A16–A23) of the address are performed with the

time-sharing.

qR/W

The Read/Write signal indicates the data bus state.

The state is read while this signal is “H” level, and

write while this signal is “L” level.

____

qBHE

“L” level is output when an odd-numbered address is

accessed.

____

qBLE

“L” level is output when an even-numbered address

is accessed.

qALE

This is used to obtain only the address from address

and data multiplex signals.

The microcomputer is in Hold state while “L” level is

_____

input to the HOLD pin.

The microcomputer is in Ready state while “L” level is

____

input to the RDY pin.

This is the

φ1 output pin.

Input/Output

Output

I/O

Output

Input

Output

Name

Address low-order/

DRAM address

Address middle-order/

data high-order

Address high-order/

data low-order

Memory control signal

output

Hold input

Ready input

Clock

φ1 output

A0/MA0–

A7/MA7

A8/D8–

A15/D15

A16/D0–

A23/D7

R/W,

____

BHE,

____

BLE,

ALE

_____

HOLD

____

RDY

φ1

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