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7721 Datasheet(PDF) 46 Page - Renesas Technology Corp |
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7721 Datasheet(HTML) 46 Page - Renesas Technology Corp |
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46 / 577 page  CENTRAL PROCESSING UNIT (CPU) 7721 Group User’s Manual 2–23 2.5 Bus access right 2.5 Bus access right The M37721’s bus is used for DRAMC, Hold function, and DMAC besides CPU. When the bus requests of two or more source are detected at the same timing, the highest bus access priority levels get the access right. The bus priority levels are fixed by hardware. Additionally the bus use state is output from the status signal output pins ST0 and ST1. Table 2.5.1 lists the bus use priority levels and the status signals depending on the bus use state. Table 2.5.1 Bus use priority levels and status signals depending on bus use state Status signal ST1 0 0 1 1 ST0 0 1 0 1 Bus use priority levels 1 (Highest) 2 3 4 (Lowest) Bus use state DRAM refresh Hold DMAC CPU (Including the term that CPU does not use the bus during calculation etc.) For details, refer to section “13.2.1 Bus access control circuit” and chapter for each peripheral devices. |
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