7721 datasheet(83/577 Pages) RENESAS

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CLOCK GENERATING CIRCUIT

7721 Group User’s Manual

5–6

(1)

Termination by interrupt request occurrence

When terminating Stop mode by interrupt request occurrence, instructions are executed after a

certain time measured by the watchdog timer has passed.

When an interrupt request occurs, the oscillator starts oscillating. Simultaneously, supply of clock

φ1, f2 to f512 starts.

The watchdog timer starts counting owing to the oscillation start. The watchdog timer counts f32

regardless of the watchdog timer frequency select bit’s (bit 0 at address 6116) contents.

When the watchdog timer’s MSB becomes “0,” supply of

φCPU and φ starts. At the same time, the

watchdog timer’s count source returns to f32 or f512 that is selected by the watchdog timer frequency

select bit.

The interrupt request which occurred in is accepted.

Table 5.3.2 lists the interrupts used to terminate Stop mode.

Table 5.3.2 Interrupts used to terminate Stop mode

5.3 Stop mode

Conditions for using each function to generate interrupt request

Interrupt

____

INTi

interrupt (i = 0 to 2)

Timer Ai interrupt (i = 2 to 4)

Timer Bi interrupt (i = 0, 1)

UARTi transmit interrupt (i = 0, 1)

UARTi receive interrupt (i = 0, 1)

In event counter mode

When external clock is selected

Notes 1: Since the oscillator has stopped oscillating, interrupts not listed above cannot be used. Also, even

the interrupts listed above cannot be used when the above conditions are not satisfied. The

A-D converter does not operate, also.

2: When multiple interrupts listed above are enabled, Stop mode is terminated by the interrupt

request which occurs first.

3: Refer to “CHAPTER 7. INTERRUPTS” and the description of each internal peripheral device for

details about each interrupt.

Before executing the STP instruction, interrupts used to terminate Stop mode must be enabled.

In addition, the interrupt priority level of the interrupt used to terminate Stop mode must be higher

than the processor interrupt priority level (IPL) of the routine where the STP instruction is executed.

When multiple interrupts in Table 5.3.2 are enabled, Stop mode is terminated by the first interrupt

request.

There is a possibility that any of all interrupt requests occurs after the oscillation starts in and until

supply of

φCPU and φ starts in . The interrupt requests which occur during this period are accepted

in order of priority after the watchdog timer’s MSB becomes “0.”

For interrupts not to be accepted, set their interrupt priority levels to level 0 (interrupt disabled)

before executing the STP instruction.

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