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7721 Datasheet(PDF) 68 Page - Renesas Technology Corp |
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7721 Datasheet(HTML) 68 Page - Renesas Technology Corp |
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68 / 577 page  7721 Group User’s Manual RESET 4–5 4.1 Hardware reset ? 0 : “0” immediately after reset. 1 : “1” immediately after reset. ? : Underfined immediately after reset. : Always “0” at reading. 0 0 : Always undefined at reading. : “0” immediately after reset. Fix this bit to “0.” 1016 1116 1216 1316 Port P8 direction register 1416 1516 1616 1716 1816 1916 1A16 1B16 1C16 1D16 1E16 1F16 016 116 216 316 416 516 616 716 816 916 B16 C16 D16 E16 F16 A16 Address Port P4 register Port P5 register Port P4 direction register Port P5 direction register Port P6 register Port P7 register Port P6 direction register Port P7 direction register Port P8 register A-D control register A-D sweep pin select register Register name Access characteristics State immediately after reset RW RW RW RW RW RW RW RW RW RW ? 0016 0016 0016 0 0 00 0 ? 11 b7 b0 b7 b0 : It is possible to read the bit state at reading. The written value becomes valid. : It is possible to read the bit state at reading. The written value becomes invalid. : The written value becomes valid. It is impossible to read the bit state. : Nothing is assigned. It is impossible to read the bit state. The written value becomes invalid. RW RO WO qSFR area (016 to 7F16, 1FC016 to 1FFF16) RW ? ? ? ? ? ? ? ? ? ? ? ? ? 0016 ? ? ? 0 ? ? ? ? ? ? ?? ? ? : Always “1” at reading. 1 ? ? ? ? ? RW RW RW RW RW WO WO Port P9 register Port P9 direction register Port P10 register Port P10 direction register Pulse output data register 0 Pulse output data register 1 00 0 00 0 00 0 00 ? Access characteristics State immediately after reset 0016 0016 Fig. 4.1.4 State of SFR and internal RAM areas immediately after reset (1) |
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