7721 datasheet(87/577 Pages) RENESAS

87 / 577 page

CLOCK GENERATING CIRCUIT

7721 Group User’s Manual

5–10

(1)

Termination by interrupt request occurrence

When an interrupt request occurs, supply of

φCPU and φ starts.

The interrupt request which occurred in is accepted.

The following interrupts are used to terminate Wait mode.

When a watchdog timer interrupt request occurs, Wait mode is also terminated.

___

•INTi interrupt (i = 0 to 2)

•Timer Ai interrupt (i = 0 to 4)

•Timer Bi interrupt (i = 0 to 2)

•UARTi transmit interrupt (i = 0, 1)

•UARTi receive interrupt (i = 0, 1)

•A-D converter interrupt

Note: Refer to “CHAPTER 7. INTERRUPTS” and each functional description about interrupts.

Before executing the WIT instruction, interrupts used to terminate Wait mode must be enabled.

In addition, the interrupt priority level of the interrupt used to terminate Wait mode must be higher

than the processor interrupt priority level (IPL) of the routine where the WIT instruction is executed.

When multiple interrupts listed above are enabled, Wait mode is terminated by the interrupt request

which occurs first.

(2)

Termination by hardware reset

The CPU and the SFR area are initialized in the same way as system reset. However, the internal

RAM area retains the same contents as that before executing the WIT instruction. The terminating

sequence is the same as the internal processing sequence which is performed after reset.

Refer to “CHAPTER 4. RESET” for details about reset.

5.4 Wait mode

7721 Datasheet(PDF) 87 Page - Renesas Technology Corp