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CLOCK GENERATING CIRCUIT

7721 Group User’s Manual

5–4

5.2 Clocks

5.2.1 Clocks generated in clock generating circuit

(1)

It is the operation clock of BIU. It is also the clock source of

φCPU.

φ stops by acceptance of Ready request or execution of the STP or WIT instruction. It is not stopped

by acceptance of bus request.

(2)

φCPU

It is the operation clock of CPU.

φCPU stops by the following:

•Execution of the STP or WIT instruction,

____

•Acceptance of Ready request; “L” level input to the RDY pin

•CPU wait request from BIU; Acceptance of bus request is included.

(3)

Clock

φ 1

It has the same period as

φ and is output to the external from the φ1 pin. Clock φ1 stops by execution

of the STP instruction.

It is not stopped by acceptance of Ready or bus request, or execution of the WIT instruction.

(4)

f2 to f512

Each of them is the internal peripheral devices’ operation clock.

Note: Refer to each functional description for details:

•Execution of STP instruction ............. “5.3 Stop mode”

•Execution of WIT instruction .............. “5.4 Wait mode”

•Ready ..................................................... “3.3 Ready function”

•Bus request ........................................... “13.2.1 Bus access control circuit”

7721 Datasheet(PDF) 81 Page - Renesas Technology Corp