7721 datasheet(36/577 Pages) RENESAS

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CENTRAL PROCESSING UNIT (CPU)

7721 Group User’s Manual

2–13

2.2 Bus interface unit

2.2.3 Operation of bus interface unit (BIU)

Figure 2.2.3 shows the basic operating waveforms of the bus interface unit (BIU).

About signals which are input/output externally when accessing external devices, refer to “CHAPTER 3.

CONNECTION WITH EXTERNAL DEVICES.”

(1)

When fetching instructions into the instruction queue buffer

When the instruction which is next fetched is located at an even address, the BIU fetches 2 bytes

at a time with the timing of waveform (a).

However, when accessing an external device which is connected with the 8-bit external data bus

width (BYTE = “H”), only 1 byte of the instruction is fetched.

When the instruction which is next fetched is located at an odd address, the BIU fetches only 1

byte with the timing of waveform (a). The contents at the even address are not taken into the

instruction queue buffer.

(2)

When reading or writing data to and from the memory•I/O device

When accessing a 16-bit data which begins at an even address, waveform (a) is applied. The 16

bits of data are accessed at a time.

When accessing a 16-bit data which begins at an odd address, waveform (b) is applied. The 16

bits of data are accessed separately in 2 operations, 8 bits at a time. Invalid data is not fetched

into the data buffer.

When accessing an 8-bit data at an even address, waveform (a) is applied. The data at the odd

address is not fetched into the data buffer.

When accessing an 8-bit data at an odd address, waveform (a) is applied. The data at the even

address is not fetched into the data buffer.

For instructions that are affected by the data length flag (m) and the index register length flag (x),

operation or is applied when flag m or x = “0”; operation or is applied when flag m or x

= “1.”

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