7477 datasheet(124/354 Pages) RENESAS

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HARDWARE

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7470/7471/7477/7478 GROUP USER’S MANUAL

1.13 Serial I/O

2 SRDY signal

The clock synchronous Serial I/O can inform the outside that a serial transfer has become ready,

by outputting the SRDY signal.

2 Transmit operation of the clock synchronous Serial I/O

The transmit operation of the clock synchronous Serial I/O is described below.

q Start of transmit operation

Transmit data is transmitted by writing it into the Transmit buffer register (TB: address 00E016)

in the transmit enable state.

When the internal clock is selected as a synchronous clock, 8 shift

clocks are generated at the time when this set value has been written.

q Transmit operation

1After transmit data is written into the Transmit buffer register,

V2 the transmit buffer empty flag

(bit 0) of the Serial I/O status register is cleared to “0.”

2The transmit data written in the Transmit buffer register is transferred to the Transmit shift

3When the data transfer from the Transmit buffer register to the Transmit shift register is completed,

the transmit buffer empty flag is set to “1.”

4The transmit data transferred to the Transmit shift register is output from the P15/TxD pin in

synchronization with the fall of the synchronous clock.

5When a transmit shift operation is started, the transmit shift completion flag (b2) of the Serial

I/O status register is cleared to “0.”

6Data is output starting with the least significant bit of the Transmit shift register. Each time one-

bit data is output, the contents of the Transmit shift register are shifted by 1 bit in the direction

of the least significant bit.

7At the time when the transmit shift operation has been completed, the Transmit shift register

shift completion flag is set to “1.”

V3 V5

V 1: Status in which the register for transmit operation has been completed. Refer to “[Clock

synchronous Serial I/O setting method]” which will be described later.

V 2: When the external clock is selected, write data into the Transmit buffer register when the

synchronous clock is at “H.”

V 3: A transmit interrupt request occurs immediately after the transfer of

2 when the transmit

interrupt source bit (bit 3) of the Serial I/O control register (SIOCON) is “0,” or at the time of

7 when the said bit is “1.”

V 4: While the transmit buffer empty flag is “1,” the next transmit data can be written into the

Transmit buffer register.

V 5: When the internal clock is used as a synchronous clock, the shift clock supply to the Transmit

shift register is automatically stopped after 8-bit data is transmitted. However, if the next

transmit data is written to the Transmit buffer register while the Transmit shift register shift

completion flag is “0,” the shift clock supply is continued and serial data is continuously

output from the TxD pin.

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