7477 datasheet(125/354 Pages) RENESAS

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HARDWARE

1-108

7470/7471/7477/7478 GROUP USER’S MANUAL

1.13 Serial I/O

__________

When using the SRDY output

__________

At the time when data has been written into the Transmit buffer register, the SRDY pin changes from

__________

“H” to “L,” informing the outside of a receive ready state. The SRDY pin is restored to “H” at the

first fall of the synchronous clock.

q Transmit interrupt operation (valid when the Serial I/O is selected)

Regarding a transmit interrupt, interrupt request generating timing can be selected by bit 3 of the

Serial I/O control register (SIOCON).

0: When the Transmit buffer register becomes empty after the data written in the Transmit buffer

1: When the shift operation of the Transmit shift register is completed, an interrupt request is

generated.

Figure 1.13B.2 shows a transmit operation of clock synchronous Serial I/O and Figure 1.13B.3

shows a transmit timing chart of clock synchronous Serial I/O.

Fig. 1.13B.2 Transmit operation of clock synchronous Serial I/O

P15/TxD

Data bus

Address 00E016

Transmit data writing

Transmit buffer register

Serial I/O status register

(Address 00E116)

Transmit buffer register

Transmit data transfer

Transmit shift register

Serial I/O status register

(Address 00E116)

Interrupt request register 1

(Address 00FC16)

Transmit shift register

Synchronous clock

When “0” is selected by the bit 3

of the Serial I/O control register

Interrupt request register 1

(Address 00FC 16)

When “1” is selected by the bit 3

of the Serial I/O control register

Serial I/O status register

(Address 00E116)

Transmit shift register

Synchronous clock

Transmit shift register

Synchronous clock

Serial I/O status register

(Address 00E116)

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