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AMUTE CONTROL

MODE CONTROL

PARALLEL HARDWARE CONTROL

PCM1691

SBAS450 – OCTOBER 2008.............................................................................................................................................................................................. www.ti.com

The PCM1691 has an AMUTE control input, status output pins, and functionality. AMUTEI is the input control pin

of the internal analog mute circuit. An AMUTEI low input causes the DAC output to cut off from the digital input

and forces it to the center level (0.5 × VCC1). AMUTEO is the status output pin of the internal analog mute

circuit. AMUTEO low indicates the analog mute control circuit is active because of a programmed condition (such

as an SCKI halt, asynchronous detect, zero detect, or by the DAC disable command) that forces the DAC

outputs to a center level. Because AMUTEI is not terminated internally and AMUTEO is an open-drain output,

pull-ups by the appropriate resistors are required for proper operation.

Additionally, because the AMUTEI pin control and power-down control in register (OPEDA[3:0] when high,

PSMDA when low) do not function together, AMUTEI takes priority over power-down control. Therefore,

power-down control is ignored during AMUTEI low, and AMUTEI low forces the DAC output to a center level (0.5

× VCC1) even if power-down control is asserted.

The PCM1691 includes three mode control interfaces with two oversampling configurations, depending on the

input state of the MODE pin, as shown in Table 9. The pull-up and pull-down resistors must each be less than 10

Ω.

Table 9. Interface Mode Control Selection

MODE

MODE CONTROL INTERFACE

Tied to DGND, low

Two-wire (I2C) serial control, selectable oversampling configuration

Left open

Two-wire parallel control, auto mode oversampling configuration

Tied to VDD, high

Three-wire (SPI) serial control, selectable oversampling configuration

The input state of the MODE pin is sampled at the moment of power-on, or during a low-to-high transition of the

RST pin, with the system clock input. Therefore, input changes after reset are ignored until the next power-on or

reset. From the mode control selection described in Table 9, the functions of four pins are changed, as shown in

Table 10.

Table 10. Pin Functions for Interface Mode

PIN ASSIGNMENTS

SPI

I2C

H/W

MD (input)

SDA (input/output)

DEMP (input)

MC (input)

SCL (input)

FMT (input)

MS (input)

ADR0 (input)

RSV (input, low)

Test (output, open)

ADR1 (input)

RSV (input, low)

In serial mode control, the actual mode control is performed by register writes (and reads) through the SPI- or

I2C-compatible serial control port. In parallel mode control, two specific functions are controlled directly through

the high/low control of two specific pins, as described in the following section.

The functions shown in Table 11 and Table 12 are controlled by two pins, DEMP and FMT, in parallel hardware

control mode. The DEMP pin controls the 44.1-kHz digital de-emphasis function of all eight channels. The FMT

pin controls the audio interface format for all eight channels.

Table 11. DEMP Functionality

DEMP

DESCRIPTION

Low

De-emphasis off

High

44.1-kHz de-emphasis on

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