PCM1691 datasheet(24/47 Pages) TI

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TIMING REQUIREMENTS

1.4V

MSH

LSB(D0)

MSS

MCH

MCL

MDS

ADR0

MSB(R/ )

MDH

MCY

MHH

TWO-WIRE (I

2C) SERIAL CONTROL

MSB

LSB

ADR1

ADR0

R/W

PCM1691

SBAS450 – OCTOBER 2008.............................................................................................................................................................................................. www.ti.com

Figure 34 shows a detailed timing diagram for the three-wire serial control interface. These timing parameters are

critical for proper control port operation.

Figure 34. Three-Wire Serial Control Interface Timing

Table 13. Timing Requirements for Figure 34

SYMBOL

PARAMETER

MIN

MAX

UNIT

tMCY

MC pulse cycle time

100

tMCL

MC low-level time

tMCH

MC high-level time

tMHH

MS high-level time

tMCY

tMSS

MS falling edge to MC rising edge

tMSH

MS rising edge from MC rising edge for LSB

tMDH

MD hold time

tMDS

MD setup time

The PCM1691 supports an I2C-compatible serial bus and data transmission protocol for fast mode configured as

a slave device. This protocol is explained in the I2C specification 2.0.

The PCM1691 has a 7-bit slave address, as shown in Figure 35. The first five bits are the most significant bits

(MSBs) of the slave address and are factory-preset to '10011'. The next two bits of the address byte are

selectable bits that can be set by MS/ADR0/RSV and TEST/ADR1/RSV. A maximum of four PCM1691s can be

connected on the same bus at any one time. Each PCM1691 responds when it receives its own slave address.

Figure 35. Slave Address

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