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EP2S15 Datasheet(PDF) 70 Page - Altera Corporation

Part # EP2S15
Description  Stratix II Device Family
PDF  238 Pages
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EP2S15 Datasheet(HTML) 70 Page - Altera Corporation

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2–62
Altera Corporation
Stratix II Device Handbook, Volume 1
May 2007
PLLs & Clock Networks
Figure 2–42. Global & Regional Clock Connections from Corner Clock Pins &
Fast PLL Outputs
Note (1)
Note to Figure 2–42:
(1)
The corner fast PLLs can also be driven through the global or regional clock
networks. The global or regional clock input can be driven by an output from
another PLL, a pin-driven dedicated global or regional clock, or through a clock
control block, provided the clock control block is fed by an output from another
PLL or a pin-driven dedicated global or regional clock. An internally generated
global signal cannot drive the PLL.



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