EP2S15 datasheet(85/238 Pages) ALTERA

85 / 238 page

Altera Corporation

2–77

May 2007

Stratix II Device Handbook, Volume 1

Stratix II Architecture

The Stratix II device IOE includes programmable delays that can be

activated to ensure input IOE register-to-logic array register transfers,

input pin-to-logic array register transfers, or output IOE register-to-pin

transfers.

A path in which a pin directly drives a register may require the delay to

ensure zero hold time, whereas a path in which a pin drives a register

through combinational logic may not require the delay. Programmable

delays exist for decreasing input-pin-to-logic-array and IOE input

automatically minimize setup time while providing a zero hold time.

Programmable delays can increase the register-to-pin delays for output

and/or output enable registers. Programmable delays are no longer

required to ensure zero hold times for logic array register-to-IOE register

transfers. The Quartus II Compiler can create the zero hold time for these

transfers. Table 2–13 shows the programmable delays for Stratix II

devices.

The IOE registers in Stratix II devices share the same source for clear or

preset. You can program preset or clear for each individual IOE. You can

also program the registers to power up high or low after configuration is

complete. If programmed to power up low, an asynchronous clear can

control the registers. If programmed to power up high, an asynchronous

preset can control the registers. This feature prevents the inadvertent

activation of another device's active-low input upon power-up. If one

must use that same signal if they require preset or clear. Additionally, a

synchronous reset signal is available for the IOE registers.

Double Data Rate I/O Pins

Stratix II devices have six registers in the IOE, which support DDR

interfacing by clocking data on both positive and negative clock edges.

The IOEs in Stratix II devices support DDR inputs, DDR outputs, and

bidirectional DDR modes.

Table 2–13. Stratix II Programmable Delay Chain

Programmable Delays

Quartus II Logic Option

Input pin to logic array delay

Input delay from pin to internal cells

Input pin to input register delay

Input delay from pin to input register

Output pin delay

Delay from output register to output pin

Output enable register tCO delay

Delay to output enable pin

EP2S15 Datasheet(PDF) 85 Page - Altera Corporation

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