EP2S15 datasheet(89/238 Pages) ALTERA

89 / 238 page

Altera Corporation

2–81

May 2007

Stratix II Device Handbook, Volume 1

Stratix II Architecture

Figure 2–55. Output TIming Diagram in DDR Mode

The Stratix II IOE operates in bidirectional DDR mode by combining the

DDR input and DDR output configurations. The negative-edge-clocked

OE register holds the OE signal inactive until the falling edge of the clock.

This is done to meet DDR SDRAM timing requirements.

External RAM Interfacing

In addition to the six I/O registers in each IOE, Stratix II devices also have

dedicated phase-shift circuitry for interfacing with external memory

interfaces. Stratix II devices support DDR and DDR2 SDRAM, QDR II

SRAM, RLDRAM II, and SDR SDRAM memory interfaces. In every

Stratix II device, the I/O banks at the top (banks 3 and 4) and bottom

(banks 7 and 8) of the device support DQ and DQS signals with DQ bus

modes of ×4, ×8/×9, ×16/×18, or ×32/×36. Table 2–14 shows the number

of DQ and DQS buses that are supported per device.

From Internal

Registers

DDR output

CLK

Table 2–14. DQS & DQ Bus Mode Support (Part 1 of 2)

Note (1)

Device

Package

Number of

×4 Groups

Number of

×8/×9 Groups

Number of

×16/×18 Groups

Number of

×32/×36 Groups

EP2S15

484-pin FineLine BGA

672-pin FineLine BGA

EP2S30

484-pin FineLine BGA

672-pin FineLine BGA

EP2S60

484-pin FineLine BGA

672-pin FineLine BGA

1,020-pin FineLine BGA

EP2S15 Datasheet(PDF) 89 Page - Altera Corporation

EP2S15 Datasheet(HTML) 89 Page - Altera Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL