EP2S15 datasheet(83/238 Pages) ALTERA

83 / 238 page

Altera Corporation

2–75

May 2007

Stratix II Device Handbook, Volume 1

Stratix II Architecture

Figure 2–50. Control Signal Selection per IOE

Notes to Figure 2–50:

(1)

Control signals ce_in, ce_out, aclr/apreset, sclr/spreset, and oe can be global signals even though their

control selection multiplexers are not directly fed by the ioe_clk[7..0] signals. The ioe_clk signals can drive

the I/O local interconnect, which then drives the control selection multiplexers.

In normal bidirectional operation, the input register can be used for input

data requiring fast setup times. The input register can have its own clock

input and clock enable separate from the OE and output registers. The

output register can be used for data requiring fast clock-to-output

performance. The OE register can be used for fast clock-to-output enable

timing. The OE and output register share the same clock source and the

same clock enable source from local interconnect in the associated LAB,

dedicated I/O clocks, and the column and row interconnects.

clk_out

ce_in

clk_in

ce_out

aclr/apreset

sclr/spreset

Dedicated I/O

Clock [7..0]

Local

Interconnect

Local

Interconnect

Local

Interconnect

Local

Interconnect

Local

Interconnect

io_oe

io_aclr

Local

Interconnect

io_sclr

io_ce_out

io_ce_in

io_clk

EP2S15 Datasheet(PDF) 83 Page - Altera Corporation

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