EP2S15 datasheet(72/238 Pages) ALTERA

72 / 238 page

2–64

Altera Corporation

Stratix II Device Handbook, Volume 1

May 2007

PLLs & Clock Networks

Figure 2–43. Global & Regional Clock Connections from Top & Bottom Clock Pins & Enhanced PLL Outputs

Notes (1), (2), and (3)

Notes to Figure 2–43:

(1)

EP2S15 and EP2S30 devices only have two enhanced PLLs (5 and 6), but the connectivity from these two PLLs to

the global and regional clock networks remains the same as shown.

(2)

If the design uses the feedback input, you lose one (or two, if FBIN is differential) external clock output pin.

(3)

The enhanced PLLs can also be driven through the global or regional clock netowrks. The global or regional clock

input can be driven by an output from another PLL, a pin-driven dedicated global or regional clock, or through a

clock control block provided the clock control block is fed by an output from another PLL or a pin-driven dedicated

global or regional clock. An internally generated global signal cannot drive the PLL.

G15

G14

G13

G12

RCLK31

RCLK30

RCLK29

RCLK28

RCLK27

RCLK26

RCLK25

RCLK24

RCLK15

RCLK14

RCLK13

RCLK12

RCLK11

RCLK10

RCLK9

RCLK8

PLL 6

CLK7

CLK6

CLK5

CLK4

PLL 12

PLL 5

c0 c1 c2 c3 c4 c5

CLK14

CLK15

CLK13

CLK12

PLL 11

PLL11_FB

PLL5_OUT[2..0]p

PLL5_OUT[2..0]n

PLL11_OUT[2..0]p

PLL11_OUT[2..0]n

PLL12_OUT[2..0]p

PLL12_OUT[2..0]n

PLL6_OUT[2..0]p

PLL6_OUT[2..0]n

PLL5_FB

PLL12_FB

PLL6_FB

Global

Clocks

Regional

Clocks

Regional

Clocks

EP2S15 Datasheet(PDF) 72 Page - Altera Corporation

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