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EP2S15 Datasheet(PDF) 81 Page - Altera Corporation |
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EP2S15 Datasheet(HTML) 81 Page - Altera Corporation |
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81 / 238 page  Altera Corporation 2–73 May 2007 Stratix II Device Handbook, Volume 1 Stratix II Architecture Figure 2–48. Column I/O Block Connection to the Interconnect Note (1) Note to Figure 2–48: (1) The 32 data and control signals consist of eight data out lines: four lines each for DDR applications io_dataouta[3..0] and io_dataoutb[3..0], four output enables io_oe[3..0], four input clock enables io_ce_in[3..0] , four output clock enables io_ce_out[3..0], four clocks io_clk[3..0], four asynchronous clear and preset signals io_aclr/apreset[3..0], and four synchronous clear and preset signals io_sclr/spreset[3..0] . 32 Data & Control Signals from Logic Array (1) Vertical I/O Block Contains up to Four IOEs I/O Block Local Interconnect IO_dataina[3:0] IO_datainb[3:0] R4 & R24 Interconnects LAB Local Interconnect C4 & C16 Interconnects 32 LAB LAB LAB io_clk[7..0] Vertical I/O Block |
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