EP2S15 datasheet(35/238 Pages) ALTERA

35 / 238 page

Altera Corporation

2–27

May 2007

Stratix II Device Handbook, Volume 1

Stratix II Architecture

C16 column interconnects span a length of 16 LABs and provide the

fastest resource for long column connections between LABs, TriMatrix

memory blocks, DSP blocks, and IOEs. C16 interconnects can cross

M-RAM blocks and also drive to row and column interconnects at every

fourth LAB. C16 interconnects drive LAB local interconnects via C4 and

R4 interconnects and do not drive LAB local interconnects directly.

All embedded blocks communicate with the logic array similar to LAB-

to-LAB interfaces. Each block (that is, TriMatrix memory and DSP blocks)

connects to row and column interconnects and has local interconnect

regions driven by row and column interconnects. These blocks also have

direct link interconnects for fast connections to and from a neighboring

LAB. All blocks are fed by the row LAB clocks, labclk[5..0].

Table 2–2 shows the Stratix II device’s routing scheme.

Table 2–2. Stratix II Device Routing Scheme (Part 1 of 2)

Source

Destination

Shared arithmetic chain

Carry chain

Local interconnect

vvvvvvv

Direct link interconnect

R4 interconnect

vvvv

R24 interconnect

vvvv

C4 interconnect

vvv

C16 interconnect

vvvv

ALM

vvvvvv

M512 RAM block

vvv

M4K RAM block

vvv

M-RAM block

vvvv

DSP blocks

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